Cache-based tracing for time travel debugging and analysis
US11138092B2 · kind B2 · utility
3Cited by
36References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2018 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jul 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is configured to record a replay-able trace of execution of an execution entity. Based on detection of a cache miss during the execution of the execution entity, the processor records an influx of data imported into a processor cache in response to the cache miss, and sets a hardware bit on a cache line of the processor cache storing the influx of data. The hardware bit indicates that the cache line has been recorded into a trace. In addition, the processor records by recording at least one side effect of the access by the execution entity to the model-specific register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.