Local cache size control in a storage array
US11138123B2 · kind B2 · utility
0Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Nov 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to: analyze input/output (I/O) operations received by a storage system; dynamically predict anticipated I/O operations of the storage system based on the analysis; and dynamically control a size of a local cache of the storage system based on the anticipated I/O operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.