Memory testing method and memory testing system
US11139044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.