Recessed inductor structure to reduce step height
US11139239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Dec 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.