Frequency independence for synthesis within programmable non-reciprocal network circuit
US11139851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Oct 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus includes parallel delay lines, each exhibiting a delay; a first set of switches for each port of a first set of ports, each of which is to selectively couple a port of the first set of ports to first ends of the delay lines; a second set of switches for each port of a second set of ports, each of which to selectively couple a port of the second set of ports to second ends of the delay lines. A signal source generates a series of clock signals that are sequentially time delayed between the first set of switches and the second set of switches, where an input signal at one of the first or second sets of ports travels back and forth across the first and second sets of delay lines according to activation of the first set and second set of switches until being output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.