Interleaving method and interleaving apparatus
US11139918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Mar 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide an interleaving method, to improve error correction performance of a polar code. In these embodiments, a first bit sequence is obtained. The first bit sequence includes L number of bits, and L is a positive integer. The L number of bits are then written into an interleaving matrix according to a preset write rule. The interleaving matrix includes C rows and R number of columns. C and R are positive integers. The L number of bits can be read from the interleaving matrix according to a preset read rule to obtain a second bit sequence. The second bit sequence includes L number of bits; and sending the second bit sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.