Gate driver circuit for reducing deadtime inefficiencies
US11144082B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Mar 30, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.