Systems and methods for dynamic configuration of a device clock
US11144086B1 · kind B1 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jan 22, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Sep 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes a programmable clock configuration block disposed at the SoC system, which manages clock frequency change flow in a single clock domain on a SoC system to provide dynamic clock frequency configuration while the SoC system is in operation. The programmable clock configuration block is configured to interact with the CPU of the SoC system to configure or change parameters relating to the clock signal frequency while the CPU is in an inactive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.