Efficient performance monitoring of integrated circuit(s) having distributed clocks
US11144087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.