System and method for evaluating memory system performance
US11144235B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | May 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.