Memory controller, memory system including the same, and method of operating the memory controller
US11144393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Apr 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.