Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereof
US11144485B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.