Optimal I3C in-band interrupt handling through reduced slave arbitration cycles
US11144490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus for serial bus arbitration are described. A data communication apparatus has a bus interface circuit that uses a line driver to couple the apparatus to a data line of a serial bus. A processor in a slave device is configured to cause the apparatus to assert an in-band interrupt request on a serial bus operated in accordance with an I3C protocol, transmit a slave address of the slave device over a data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted, ignore signaling state of the data line while transmitting the slave address and participate in one or more transactions conducted responsive to assertion of the in-band interrupt request and transmission of the slave address. At least one other slave device transmits an address over the data line during the first bus arbitration transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.