System with secure SoC connections among IP and multiple GPIOs, and corresponding method
US11144678B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 8, 2018 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Nov 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.