Method implemented on computer system executing instructions for semiconductor design simulation
US11144699B2 · kind B2 · utility
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24References
20Claims
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Key dates
| Filing date | Sep 11, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Sep 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.