Gate dielectric preserving gate cut process
US11145536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.