Method of fabricating a chip package module with improve heat dissipation effect
US11145565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Jun 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/166
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.