Process for forming metal-insulator-metal structures
US11145592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Feb 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.