Semiconductor chip including alignment pattern
US11145601B2 · kind B2 · utility
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2References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 4, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Mar 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.