Patent · US Active

Uncore input/output latency analysis

US11151011B2 · kind B2 · utility

0Cited by
5References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 1, 2019
Grant dateOct 19, 2021
Priority date
Expiry dateOct 1, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2201/835
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A computing system includes a core system and an uncore system. The core system includes a packet generator unit configured to generate a data packet having a plurality of bytes defining a target packet size, and to output a first byte among the plurality of bytes at a packet delivery start time. The uncore system includes an input/output (I/O) bridge configured to connect an I/O component to the core system, and a packet monitor unit configured to monitor the bytes delivered from the packet generator unit to the I/O component. The packet monitor unit further determines a packet delivery end time after detecting a last byte of the data packet. The computing system determines a latency attributed to the uncore system and the I/O bridge based on the packet delivery start time and the packet delivery end time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.