System and method for managing requests in an asynchronous pipeline
US11151287B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 7, 2018 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Jan 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.