Memory cell array circuit
US11151296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | May 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/841
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.