Computing in-memory system and method based on skyrmion racetrack memory
US11151439B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 25, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.