Memory device, memory cell and method for programming memory cell
US11152064B2 · kind B2 · utility
1Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Jan 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.