Method of forming an interconnect in a semiconductor device
US11152258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Sep 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/05569
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes patterning a dielectric layer to form a groove and depositing a plurality of conductive layers over the dielectric layer and in the groove. The first conductive layer is a liner layer, the second conductive layer is a metal film, and the third conductive layer is a capping layer. The first conductive layer is treated with a hydrogen plasma treatment to remove impurities. The first conductive layer is also treated with a hydrogen soak treatment to remove microvoids. The third conductive layer is treated with an ammonia plasma treatment to remove impurities. The third conductive layer is also treated with a hydrogen plasma treatment to remove additional impurities. The third conductive layer is also treated with a hydrogen soak treatment to remove microvoids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.