Monolithic multi-FETs
US11152395B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2020 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/36
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.