Display panel for reducing coupling capacitance between gate of driving transistor and data line and display device
US11152445B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Apr 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
Abstract
The present disclosure provides a display panel and a display device. The display panel includes pixel circuits arranged in a matrix, and a blocking unit. Each pixel circuit includes: a driving transistor; a first switch transistor; a second switch transistor; and a third switch transistor. The blocking unit is configured to receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion, the first semiconductor connection portion is connected between a second electrode of the first switch transistor and a gate electrode of the driving transistor, and the second semiconductor connection portion is electrically connected between a first electrode of the second switch transistor and a data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.