Feedback control for accurate signal generation
US11152947B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Feb 20, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.