Systems and methods for chassis-level persistent memory sequencing and safety
US11157060B2 · kind B2 · utility
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Key dates
| Filing date | Sep 11, 2018 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jul 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/1492
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method may include, in a chassis configured to provide a common hardware infrastructure to one or more modular information handling systems inserted into the chassis: determining if a save operation is occurring at a time when one or more power supply units are capable of delivering power to the chassis; and delaying power sequencing of the one or more power supply units until the save operation has completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.