Memory systems and operating methods of memory systems
US11157342B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 18, 2018 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Dec 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.