Multi-chip module rate adjustment
US11157433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jan 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.