Patent · US Active

Graph partitioning and placement for multi-chip neurosynaptic networks

US11157795B2 · kind B2 · utility

1Cited by

0References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Arnon Amir · Saratoga, US
Pallab Datta · San Jose, US
Myron D. Flickner · San Jose, US
Dharmendra S. Modha · San Jose, US
Tapan K. Nayak · New Delhi, IN

Key dates

Filing date	Mar 13, 2017
Grant date	Oct 26, 2021
Priority date	—
Expiry date	Jul 7, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06N20/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.