Device-region layout for embedded flash
US11158377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Nov 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.