Semiconductor package including a backside redistribution layer
US11158579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2019 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jan 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a frame having a cavity and having a wiring structure connecting first and second surfaces opposing each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip; and a second redistribution layer having a redistribution pattern and a connection via connecting the wiring structure and the redistribution pattern. The connection via includes a first via connected to the wiring structure and a second via disposed on the first via and connected to the redistribution pattern, a lower surface of the second via has an area larger than an area of an upper surface of the first via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.