Decorrelation of intermodulation products in mixer circuits
US11158941B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2019 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jun 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for decorrelation of intermodulation products in mixer circuits. A circuit implementing the techniques according to an embodiment includes four switches. Each of the switches comprise a complementary pair of n-channel and p-channel metal oxide semiconductor (NMOS/PMOS) field effect transistors (FETs). The NMOS/PMOS FETs include a source port, a drain port, and a gate port. The gate port is configured to receive an oscillator signal. The circuit also includes electrical conductors to couple the four switches into a double-balanced passive ring configuration to generate an output signal as a mix of an input signal and the oscillator signal. The output signal includes a third order intermodulation (IM3) product. The circuit further includes a voltage bias generator to generate a bias voltage to bias the input signal and the output signal. The magnitude and phase of the IM3 product are determined, at least in part, by the bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.