Hybrid FIFO buffer
US11159148B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | May 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.