Background calibration of non-linearity of samplers and amplifiers in ADCs
US11159169B2 · kind B2 · utility
1Cited by
6References
20Claims
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Key dates
| Filing date | May 18, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.