Seamless bit-level low-latency retimer for data links
US11159353B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2021 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Mar 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. A first sequence of data packets is transferred via the bit level data path of the retimer. While transferring the first sequence of data packets, the data link detects initiation of an equalization procedure based on an initiation data packet in the first sequence of data packets. In accordance with detection of the initiation of the equalization procedure, the data link selects the full data path of the retimer for data transfer over the data link. During the equalization procedure, a second sequence of data packets immediately follows the first sequence of data packets, and is transferred via the full data path of the retimer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.