Packet processing device and packet processing method
US11159444B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2019 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Oct 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet processing device includes a first unit, a second unit, and a switching unit. The first unit counts the number of arrived packets in a first period that is from the time slot present after a priority section up to the end of the initial time slot in the subsequently-arriving priority section. When the counted number of arrived packets is positive, the first unit determines that forward mismatch has occurred in an observation cycle. The second unit counts the number of arrived packets in a second period which is from the time slot present immediately after the priority section in the first period of time up to the end of the initial time slot of burst sections in the subsequently-arriving priority section. When the counted number of arrived packets is “0”, the second unit determines that backward mismatch has occurred in the observation cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.