Fiber attach enabled wafer level fanout
US11163120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Nov 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/18
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.