Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch
US11163578B2 · kind B2 · utility
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3References
12Claims
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Key dates
| Filing date | Feb 23, 2018 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jun 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for reducing register bank conflicts based on software hint and hardware thread switch are disclosed. In some embodiments, an apparatus for thread switching includes a graphics processing unit (GPU) that includes a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts. Decoding circuitry checks a thread switching field of a first instruction to be executed by a first thread. The GPU performs a thread switch mechanism to cause a second instruction to be executed by a second thread when the thread switching field of the first instruction is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.