Securing microprocessors against information leakage and physical tampering
US11163857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Aug 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.