Integrated circuits and methods of forming integrated circuits
US11164858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Mar 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/206
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.