Electrostatic discharge protection circuit and electronic device thereof
US11164860B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 11, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Mar 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrostatic discharge protection circuit and a semiconductor device are provided. The circuit includes: a power source terminal, a ground terminal, and a discharge path. The discharge path includes a clamp transistor and a MOS transistor connected in series and integrated into a same semiconductor substrate with different types. For the MOS transistor, a gate electrode is electrically connected to a substrate terminal; a first electrode is one of a source electrode and a drain electrode; a second electrode is another one of the source electrode and the drain electrode; the first electrode is electrically connected to a gate electrode of the clamp transistor; and the second electrode is electrically connected to the ground terminal. When an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.