Vertical memory devices and methods of manufacturing the same
US11164887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | May 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.