Array substrate, method for manufacturing the same, display panel and display device
US11164895B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 19, 2017 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | May 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an array substrate, a method for manufacturing the same, a display panel, and a display device. The array substrate includes: a gate metal layer, disposed on the substrate and the gate metal layer including a grounding wire located in the peripheral region; a gate insulating layer, at least covering the gate metal layer; and a conductive layer structure, disposed over the gate insulating layer and including an auxiliary grounding wire located in the peripheral region, wherein the auxiliary grounding wire is connected to the grounding wire. The present disclosure can prevent ESD more effectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.