Method for forming a passivating electrical contact on a crystalline semiconductor substrate and device comprising such contact
US11164981B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/547
Abstract
A method includes depositing a first layer including amorphous silicon on a surface of a substrate; depositing a second layer including metal on the first layer; and performing an annealing process at a temperature within a range of 70° C. to 200° C., thereby inducing a silicidation reaction between the first layer and the second layer and forming a third layer comprising a metal silicide in electrical contact with the substrate, resulting in a remaining part of the first layer being between the substrate and the third layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.