System and method for correlated double sampling
US11165981B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jul 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for correlated double sampling is disclosed. In one aspect, the circuit comprises a reset switch connected with an input node, and with a first node of a first capacitor; a sampling switch connected with the input node, and with a first node of a second capacitor; a second node of the first/second capacitor is adapted to be connected with a first/second reference node, of which at least one using a reference switch; a first switch connected between the second node of the first capacitor and the first node of the second capacitor; a second switch connected between the first node of the first capacitor and the second node of the second capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.