Time synchronization of distributed devices
US11166250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Mar 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system of synchronizing a local clock with a master clock using a serial communication bus includes receiving by a serial data interface receiver a master time signal corresponding to a master clock, generating by a frequency tuning loop a time error signal corresponding to a difference between the master time signal and a local time signal, generating by the frequency tuning loop an actual frequency signal based on a base frequency and the time error signal, producing by the frequency tuning loop a command frequency error based on the actual frequency signal and the local time signal, and producing by the local clock an updated local time signal based on the command frequency error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.