Technologies for verifying a de-embedder for interconnect measurement
US11169194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Feb 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R27/28
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.